1. Field of the Invention
This invention relates to a self-aligned contact and interconnect structure, and method for making same, for use in integrated circuits and particularly in CMOS integrated circuits, having broad applicability in both memory and logic products. More specifically, the invention relates to integrated circuit multi-layer local interconnections where the transistors are self-aligned and a relatively thick planarization layer is formed over the entire surface of the substrate.
2. Description of The Prior Art
In U.S. Pat. No. 5,166,771 (incorporated herein by reference) issued Nov. 24, 1992 and entitled "Self-Aligning Contact and Interconnect Structure", Norman Godinho et al. describe a self-aligned contact structure which allows for high packing density (i.e., more transistors per unit area) of integrated circuits without forcing the production process to finer line geometries and hence higher cost.
The self-aligning source and drain contacts described therein overlap the gate electrode, without shorting the source or the drain to the gate electrode. This overlapping also allows for a looser alignment tolerance requirement thus allowing a smaller size transistor.
Contacts to the polycrystalline silicon ("polysilicon") gate are made on top of the gate region over the active channel, because the source and drain regions are protected by a hardened layer of photoresist during etching of the insulation to expose the gate contact. This allows a reduction in the size of the field of the device which saves valuable silicon area and allows a higher packing density to be obtained in a given integrated circuit.
In one embodiment a layer of titanium silicide covered by a thin film of titanium nitride is formed on the exposed source, drain and polysilicon gate contacts. The silicided areas are formed only in selected locations.
The second layer of polysilicon is deposited and patterned to form local interconnects. The etching process to define the local interconnects does not attack the exposed underlying silicided source, drain and gate contacts in the interconnects. Therefore, the polysilicon local interconnect layer is not required to completely cover and protect the source, drain and gate contacts in the interconnects, reducing alignment tolerance and saving space.
However, this patent (and other well known prior art using self-alignment without surface planarization and high topography) faces the typical problem that as an integrated circuit layout area is reduced it becomes more difficult to ensure a stringer-free (without local bridging) interconnect. This is because of the relatively tight gaps created. Current planarization techniques require the layout area to be enlarged, to allow the local interconnects to make contact to the underlying conductors. This is because as the valleys (for instance between the gate structures) are filled with a planarizing dielectric, it becomes difficult to make electrical contact to the bottoms of the valleys while simultaneously extending the electrical contacts to the tops of the gate structures, without sacrificing semiconductor fabrication process margin.
It is possible to form a self-aligned transistor using relatively small layout areas using interconnects through a thin isolation layers. However, problematically in such a case the surface is not planar due to the relatively thin dielectric, and this results in a relatively high topology, i.e. the gate structures are relatively high steps above the semiconductor substrate surface. In this case when relatively narrow interconnect lines are formed there is frequently a problem with bridging, in that stringers are left on the steps overlying the gate structures. The extreme over etches needed to remove such stringers often undesirably break the continuity of the local interconnect lines.
Therefore, with most prior art self-alignment techniques it is almost impossible to use a thick planarizing dielectric, because such a thick dielectric reduces the process margins, causing one conductor to undesirably contact another conductor in spite of the self-alignment. (In this case, typically a thin planarization dielectric is approximately 1000 to 1500 .ANG. thickness or less, and a thick dielectric is anything greater in thickness.)
Thus in the prior art, local planarization for transistor fabrication is contradictory to self-alignment schemes. It would be desirable to combine the two so as to achieve both the relative economy of self-alignment techniques which reduce the number of masking steps, with the advantages of a planarized surface which allows formation of relatively tight pitched narrow interconnect lines. Planarization is important because it overcomes the continuity problems caused by severe (non-planar) topography, such as varying resistance across a vertical step portions during implantation and poor coverage over a vertical step during silicidization (such as of titanium) or any sputtered metal layer. This combination of self-alignment and local planarization is especially important in semiconductor fabrication techniques using multi-layer local interconnections below the first major and middle interconnect layer, such as used in a planarized BPSG (boro-phosphosilicate glass) or SOG (spun on glass) or CMP (chemically mechanically polished) planarized surface.
In U.S. Pat. No. 5,340,774 (incorporated herein by reference) issued Aug. 23, 1994 and entitled "Semiconductor Fabrication Technique Using Local Planarization with Self-Aligned Transistors", Ting-Pwu Yen describes formation of self-aligned transistors while providing local planarization of the surface of the integrated circuit over the self-aligned transistors. This disclosure provides partial planarization by using an oxide layer and planarizing filler layer, such as reflowed BPSG, over the substrate surface and over the gate structures. The filler layer is etched down to the oxide layer but remains in the valleys between gate structures to planarize the area around a transistors. A polysilicon layer is then formed over the planarized surface. Then portions of the polysilicon and filler layer are removed with an additional polysilicon masking step to allow a buried contact to connect with the active regions of the transistors. Then a polysilicon isolation mask is used to allow contact to the gate structure. Since the filler layer has planarized the area between the buried contact and the gate structure, local interconnects can be formed free of bridging in self-alignment schemes.
However, this method provides only partial local planarization so that additional layers above the local interconnect will suffer the problems described above. In addition the process described in Yen requires an additional masking step which would increase the cost of fabricating ICs using this process. Furthermore, the buried contact region formed through the filler layer is narrow and deep; therefore, it is difficult to make adequate contact to the active regions of the transistors. Consequently, the local interconnect may have a high resistance at that junction.